Notes on MIPS Instruction Encoding

[Iconoclast]

My work in test. Please suggest informational additions or corrections and feedback on the style of the content.

I wrote the reference card and notes to make understanding MIPS disassembly easier by removing the detailed focus as to which MIPS instruction set architecture "ISA" is being used. Please note that, where it says "Conventions of MIPS32 Instructions", the information's application is not limited to only the MIPS32 ISA but all MIPS ISAs released before it (as well as the enhancement revision MIPS32r2 ISA that MIPS developed in response to consumer needs), because every ISA released by MIPS was developed under the scale of backwards compatibility. MIPS64, however, allows for 64-bit instructions, but the information on the right half of the reference picture still applies to those instructions.

Some video-gaming platforms that execute MIPS instructions are:

• Nintendo 64
• PlayStation
• PlayStation 2
• PlayStation Portable

These things are consistent:

• An operation code "op-code" is identified by a number that is always 6 bits long, creating 64 possibilities of operation codes whose identifier binary numbers are of the range 000000-111111.
• The 32 general-purpose registers "GPRs" can all be numbered using 5-bit identifier numbers of the range 00000-11111.
• The source, destination, and target registers used by any instruction can only be GPRs.
• The shift amount is only used by shift functions of register-encoded instructions.
• The target address for jump-type instructions is measured in the nybble unit. Shift this value 2 bits to the left to form the target address measured in bits.

In theory, some rules can be bent by future developers who modify either the MIPS32 or MIPS32r2 ISA. For all ISAs that are not extended upon or modified by developers since their original release, these rules hold true.

Of any MIPS instruction, there are three forms.

• Immediate-encoded "I-type" instructions execute to do a function--determined by an operation code--whose parameters are a source register, a target destination register or which function to do if the operation code is REGIMM, and a signed 16-bit data number called the "immediate".
• Jump-encoded "J-type" instructions execute to update the program counter (PC) special register with a new instruction index, and the other operand is the first bit of the operation code--which is either J (000010) or JAL (000011)--determining whether to link the current address to the return address ($ra) GPR before jumping.
• Register-encoded "R-type" instructions execute to do a register function--determined by the SPECIAL operation code and always more specifically by the first 6 bits of the machine code identifying the instruction--whose parameters are a source register, a target source register, a destination register, and a shift amount.

The first MIPS GPR, the ZERO register, is simply hardwired to 0. Since its value cannot be changed, it can be used as a source register if you want to work with the number 0 in a function or a destination register to discard data. Not every ISA has a ZERO register, but the MIPS architecture implemented it on MIPS ISAs to allow for better CPU performance.

For documentation on specific MIPS ISAs, check the MIPS Technologies, Inc. website.

 

[Iconoclast]

Okay just updating this with some informational fixes.
Re-uploading the image won't really announce where I was wrong which is why I submit in the form of this post instead.

And I realize that probably no one cares about my thread , but if it suits moderator judgement do merge the posts.
Just taking notes for now.

"Conventions of MIPS32 Instructions"
When I wrote this image, I wasn't yet fully versed outside of simple historical modifications for each MIPS ISA. The bit-encoding conventions, however, apply to all MIPS instructions, for any ISA released under the MIPS architecture.
I was then falsely under the impression that MIPS64 meant support for 64-bit MIPS instructions. MIPS64, actually, means you can work with 64-bit numbers in registers or operate in 32-bit mode. I'm not sure offhand about PSX, but I know that N64 uses the MIPS64 architecture, through the VR4300 processor.

In the image I defined the opcode for register-encoded functions as 000000. This, indeed, is the only opcode defining the format as register-encoded, but I presumed at the time that there was no other way to create this kind of instruction. Coprocessor instructions, though, are sometimes R-type instructions under the instruction field classes defined by the COP[z] opcodes.

That's all for would-be modifications to the GIF I posted. Currently I'm writing an extended documentation covering all MIPS instructions using linear bitstring tables on the r4300i microprocessor and listings of the CPU registers, CP0 registers, and FPU registers. It's really cool, I think, and includes corrective (grammar and otherwise) naming of each instruction and field class name, information about class acronyms that is hard to extract from any official manual by MIPS. I think my work in progress is coming out as an agreeable source that is useful as a convenient reference for if you want to write basic N64 applications in machine code.